Digital information transmitted from a sending station to a receiving station may be protected from errors by developing code related to the individual bits comprising a message, appending the code to the original message and transmitting the message and the code to the receiving station, and then generating code at the receiving station to check for corrupted data. Because the code is related to the original message bits through a generating polynomial, the code bits are considered redundant to the message bits used to generate them. Therefore, a process which uses polynomial division to generate redundant bits is referred to as cyclical redundancy code (CRC). Typically, messages are coded bitwise in hardware, the CRC generating polynomial function provided for by utilizing linear feedback shift registers.
CRC generation in software utilizes CRC generating lookup tables, instead of shift registers, to generate the applicable CRC code. Message bits are analyzed and compared to a CRC value contained in the CRC generating lookup table, the corresponding value representing the CRC checkbit value that is appended to the original message. However, CRC generation in software is inherently slower than the hardware implementation, even when performed over several message bits concurrently. Further, prior art methods for CRC generation in software are subject to the restriction that the degree of the generating polynomial cannot exceed the size of the message unit to which it is applied.